A Young Engineer's Primer to SKC's HASP
	- with apologies to Neal Stephenson and his A Young Lady's Primer

Descision of FPGA vs OMAP
	Decision Metrics
		Power consumption
		Processing Power
		Design Complexity

	OMAP
		Connectors a negative
	FPGA
		Design Complexity a negative

Camera Sensor 
	Basic Functionality
		Wikipedia on comparing CCD and CMOS Image Detectors 						(http://en.wikipedia.org/wiki/Active_pixel_sensor#Comparison_to_CCDs)
		CCD vs. CMOS: Facts and Fiction
			www.dalsa.com/public/corp/Photonics_Spectra_CCDvsCMOS_Litwiller.pdf 
	Interfaces
		Output via Parallel
		Input & ? Output via I2C
			? Do we need I2C read capability
	MTM Clock Speed

	External Clock to Pixel Speed
		Pg 92 of the MT9M131 datasheet shows Clock Generation
			on the Head Board schematic the MT9M131 part refers to the EXTCLK as CLK_IN
		Lab tests show the Head Board outputting a PXCLK of 1.471MHz while running on the 48MHz Oscillator

Power Subsystem
	Choice Metrics for DC to DC Converter
	DC to DC Converter
	Control Board Regulation


Connection to HASP Main
	Interface connectors
		Control
		Power

Mechanical
	Enclosure/Baffle
	Subplatform Heatsink
	ICs to Heatsinking 

Thermal 
	Temperature Sensors
		On Baffle Housing & Heat Sinks
		Baffle Housing Sensor Range 

Schematic Entry

PCB Layout
	Footprints
 

Software 
	Image Sensor
		Control Signals to Sensor Chip or I2C Driver Software
		Data from Sensor Chip
			FPGA reads 8 data lines route directly to flash or processor
	HASP Interface
	System Monitoring
	Interrupt Task Manager

Program Memory Storage (NVRAM ROM)
	ROM Mode
		Cyclone III device family M9K memory blocks support ROM mode. A .mif initializes
		the ROM contents of these blocks. The address lines of the ROM are registered. The
		outputs can be registered or unregistered. The ROM read operation is identical to the
		read operation in the single-port RAM configuration.

		Cyclone III Device Handbook, Volume 1 pg 3-14

	Device 	Logic		Number of	Total RAM	18 x 18		PLLs	Global Clock	Maximum
		Elements	M9K Blocks	Bits		Multipliers		Networks	User I/Os
	EP3C25 	24,624 		66 		608,256 	66 		4 	20 		215
		Cyclone III Device Handbook, Volume 1 pg 1-3


Configuring FPGA 
	pg 3-4 of chapter 3 of Serial Configuration Devices (EPCS1,EPCS4, EPCS16, EPCS64, and EPCS128) Data She3et
	shows a nice schematic connecting an EPCS16SI16N configuration device to a CycloneŽ III EP3C25 Device

	http://www.altera.com/literature/hb/cfg/cyc_c51014.pdf

	Pinouts for the CycloneŽ III EP3C25 Device are available at
	http://www.altera.com/literature/dp/cyclone3/EP3C25.pdf

NIOS II Instruction Performance
	Nios II Processor Reference Handbook pg 5-11
		Branch correctly predicted taken 2 cycles
		Normal ALU instructions (e.g., add, cmplt) 1 cycle

	Nios II Processor Reference Handbook pg 5-19
		Executes at most one instruction per six clock cycles